Texas Instruments /MSP432P4011 /DMA /DMA_PRIOCLR

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Interpret as DMA_PRIOCLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLR_0)CLR

CLR=CLR_0

Description

Channel Priority Clear Register

Fields

CLR

Set the appropriate bit to select the default priority level for the

specified DMA channel.

0 (CLR_0): No effect.

Use the DMA_PRIOSET Register to set channel C to the high priority level.

1 (CLR_1): Channel C uses the default priority level.

Writing to a bit where a DMA channel is not implemented has no effect.

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